1. Field of the Invention
The disclosure relates to a driver circuit for driving an active matrix driving display device and an active matrix driving display device having the driver circuit, and more particularly to a driver circuit that enhances the display quality of a display device and a liquid crystal display device having the driver circuit.
2. Description of the Related Art
Generally, a polycrystalline liquid crystal display (LCD) device has a high operation speed and consumes low power, but many processes of manufacturing the polycrystalline LCD device are required. The polycrystalline LCD device is used usually in display devices having a small screen size. An amorphous LCD device is used usually in display devices having a large screen size, for example, lap top computers (or notebook computers), LCD monitors, high definition televisions (HDTV's).
Recently, the amorphous LCD device employs a gate driver circuit formed on a glass substrate (or thin film transistor substrate) of an LCD panel so as to reduce the steps of manufacturing the LCD device.
Generally, the gate driver circuit includes a shift register and wiring part. The wiring part provides the shift register with a plurality of signals. The wiring part includes a plurality of wirings, and the layout of the wirings affects the output signals outputted from the gate driver circuit. The output signals from the gate driver circuit may be distorted due to the capacitance induced by the wirings crossing each other. Accordingly, the display quality of the LCD device is lowered.
The conventional gate driver circuit formed on the thin film transistor (TFT) substrate has the following problems when the gate driver circuit is employed in the amorphous LCD device having a large screen size and high resolution.
According as the screen size of the LCD device becomes larger and the resolution of the LCD device becomes higher, the number of the gate lines and the pixels formed on the TFT substrate increases. According as the number of the gate lines and the pixels increases, the father the gate line are spaced apart from the gate driver, the larger is the RC delay of the gate line. The high level period of a clock signal on the last gate line is delayed large enough to cause the distortion of the output signal compared with the high level period of a clock signal on the first gate line. Therefore the display quality is deteriorated.
In addition, a capacitance is generated between the wirings disposed the farthest from the driver circuit and having a large line width. Accordingly, the RC delay of the wirings increases. Therefore, there is required a wiring structure in which the delay of the gate driving signal transmitted to the gate line is minimized.